DESIGN ENGINEER

As a design engineer on our Design team, you will have the opportunity to work with one of our product divisions to develop our next generation of best-in-class silicon products. Opportunities exist in the areas of circuits, high-level logic, and mixed-signal devices.

Circuit Designer: As a circuit-level designer, you may have the opportunity to participate in any of the following: Specification, Design, Schematic Capture, and Layout of CMOS circuits, simulation with Spice and behavioral mixed-signal simulators, development of analog and mixed-signal IP chip development with industry-leading CAD tools

Logic Designer: As a logic designer you may have the opportunity to participate in any of the following: design of high-level logic functions using Verilog, use of Design Compiler to implement those functions, solving timing, power, and speed issues with industry-leading CAD tools.

Mixed-Signal Designer: As part of the Mixed-Signal Development and Verification team, you will learn mixed-signal verification flow and contribute to the development of Cypress’ leading-edge mixed signal products. And, as part of the Design Team, you will contribute to and be responsible for implementation and verification of key DFT logic modules. You will also contribute in various tasks spanning the entire design process.

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Electrical Design Engineer Principal (ASIC Design, RTL, Front End) Bangalore, KA, IN Dec 12, 2017
Staff Mask Design Engr 1
Staff Mask Design Engr 1 Bangalore, KA, IN Dec 11, 2017
Bangalore, KA, IN Dec 11, 2017
Sr Prin Elect Design Engr
Sr Prin Elect Design Engr San Jose, CA, US Dec 11, 2017
San Jose, CA, US Dec 11, 2017
Elect Design Engr
Elect Design Engr San Jose, CA, US Dec 10, 2017
San Jose, CA, US Dec 10, 2017
Sr MTS Architect
Sr MTS Architect San Jose, CA, US Dec 9, 2017
San Jose, CA, US Dec 9, 2017
Staff/Senior Staff Mask Design Engr (Analog/Mixed Signal Layout, Mask Design) Bangalore, KA, IN Dec 9, 2017
Sr Elect Design Engr
Sr Elect Design Engr Bangalore, KA, IN Dec 8, 2017
Bangalore, KA, IN Dec 8, 2017
Staff Elect Design Engr
Staff Elect Design Engr San Jose, CA, US Dec 8, 2017
San Jose, CA, US Dec 8, 2017
Elect Design Engr
Elect Design Engr San Jose, CA, US Dec 8, 2017
San Jose, CA, US Dec 8, 2017
Sr Prin Systems Engr (MAC)
Sr Prin Systems Engr (MAC) Bangalore, KA, IN Dec 7, 2017
Bangalore, KA, IN Dec 7, 2017
Sr Mask Design Engr
Sr Mask Design Engr Penang, 07, MY Dec 7, 2017
Penang, 07, MY Dec 7, 2017
Elect Design Engr
Elect Design Engr Cork, C, IE Dec 7, 2017
Cork, C, IE Dec 7, 2017
Sr Prin Elect Design Engr
Sr Prin Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
Prin Elect Design Engr
Prin Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
Staff Elect Design Engr
Staff Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
Staff Elect Design Engr
Staff Elect Design Engr Dublin, D, IE Dec 7, 2017
Dublin, D, IE Dec 7, 2017
ASIC Design Engr (RTL Design) - Principal Design Engineer Bangalore, KA, IN Dec 6, 2017
Sr Prin Systems Engr
Sr Prin Systems Engr Hsinchui, HSQ, TW Dec 6, 2017
Hsinchui, HSQ, TW Dec 6, 2017
Sr Elect Design Engr (Circuit Design, Mixed Signal) Bangalore, KA, IN Dec 5, 2017
Prin Systems Engr 1 1
Prin Systems Engr 1 1 Taipei, TPQ, TW Dec 4, 2017
Taipei, TPQ, TW Dec 4, 2017
Staff Elect Design Engr
Staff Elect Design Engr Martinsried, BY, DE Dec 4, 2017
Martinsried, BY, DE Dec 4, 2017
Sr Staff Elect Design Engr (STA, Timing Analysis, Timing Closure, Constraints) Bangalore, KA, IN Dec 3, 2017
Sr Product Engr
Sr Product Engr Bangalore, KA, IN Dec 3, 2017
Bangalore, KA, IN Dec 3, 2017