DESIGN ENGINEER

As a design engineer on our Design team, you will have the opportunity to work with one of our product divisions to develop our next generation of best-in-class silicon products. Opportunities exist in the areas of circuits, high-level logic, and mixed-signal devices.

Circuit Designer: As a circuit-level designer, you may have the opportunity to participate in any of the following: Specification, Design, Schematic Capture, and Layout of CMOS circuits, simulation with Spice and behavioral mixed-signal simulators, development of analog and mixed-signal IP chip development with industry-leading CAD tools

Logic Designer: As a logic designer you may have the opportunity to participate in any of the following: design of high-level logic functions using Verilog, use of Design Compiler to implement those functions, solving timing, power, and speed issues with industry-leading CAD tools.

Mixed-Signal Designer: As part of the Mixed-Signal Development and Verification team, you will learn mixed-signal verification flow and contribute to the development of Cypress’ leading-edge mixed signal products. And, as part of the Design Team, you will contribute to and be responsible for implementation and verification of key DFT logic modules. You will also contribute in various tasks spanning the entire design process.

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Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Apr 26, 2017
Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Apr 26, 2017
Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Apr 26, 2017
Staff Elect Design Engr
Staff Elect Design Engr San Jose, CA, US Apr 25, 2017
San Jose, CA, US Apr 25, 2017
Sr Principal Architect
Sr Principal Architect San Jose, CA, US Apr 24, 2017
San Jose, CA, US Apr 24, 2017
Staff ASIC Design Engr
Staff ASIC Design Engr Tel Aviv, TA, IL Apr 24, 2017
Tel Aviv, TA, IL Apr 24, 2017
Sr Elect Design Engr
Sr Elect Design Engr Tel Aviv, TA, IL Apr 24, 2017
Tel Aviv, TA, IL Apr 24, 2017
Sr MTS Architect
Sr MTS Architect San Jose, CA, US Apr 22, 2017
San Jose, CA, US Apr 22, 2017
Staff Mixed Signal Verification Engr
Staff Mixed Signal Verification Engr Bangalore, KA, IN Apr 21, 2017
Bangalore, KA, IN Apr 21, 2017
Sr Staff Elect Design Engr (SoC Verification, OVM, UVM) Bangalore, KA, IN Apr 21, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Dublin, D, IE Apr 20, 2017
Dublin, D, IE Apr 20, 2017
Prin Elect Design Engr (WLAN PHY Verification)
Prin Elect Design Engr (WLAN PHY Verification) Bangalore, KA, IN Apr 20, 2017
Bangalore, KA, IN Apr 20, 2017
Elect Design Engr
Elect Design Engr Colorado Springs, CO, US Apr 18, 2017
Colorado Springs, CO, US Apr 18, 2017
Staff RFIC Design Engineer
Staff RFIC Design Engineer San Jose, CA, US Apr 18, 2017
San Jose, CA, US Apr 18, 2017
Sr Staff Systems Engr
Sr Staff Systems Engr Hsinchui, HSQ, TW Apr 18, 2017
Hsinchui, HSQ, TW Apr 18, 2017
Sr Staff Systems Engr
Sr Staff Systems Engr Hsinchui, HSQ, TW Apr 18, 2017
Hsinchui, HSQ, TW Apr 18, 2017
Sr Prin Systems Engr
Sr Prin Systems Engr Hsinchui, HSQ, TW Apr 18, 2017
Hsinchui, HSQ, TW Apr 18, 2017
Sr Prin Systems Engr
Sr Prin Systems Engr Hsinchui, HSQ, TW Apr 18, 2017
Hsinchui, HSQ, TW Apr 18, 2017
Prin ASIC Design Engr (SoC Verification, OVM, UVM, System Verilog) Bangalore, KA, IN Apr 18, 2017
CAD Engr
CAD Engr Lexington, KY, US Apr 18, 2017
Lexington, KY, US Apr 18, 2017
Staff Elect Design Engr
Staff Elect Design Engr Bangalore, KA, IN Apr 15, 2017
Bangalore, KA, IN Apr 15, 2017
Staff Elect Design Engr
Staff Elect Design Engr Bangalore, KA, IN Apr 15, 2017
Bangalore, KA, IN Apr 15, 2017
Elect Design Engr
Elect Design Engr Martinsried, HE, DE Apr 15, 2017
Martinsried, HE, DE Apr 15, 2017
Sr Staff ASIC Design Engr
Sr Staff ASIC Design Engr Bangalore, KA, IN Apr 15, 2017
Bangalore, KA, IN Apr 15, 2017
Staff Elect Design Engr (Physical Design)
Staff Elect Design Engr (Physical Design) Bangalore, KA, IN Apr 15, 2017
Bangalore, KA, IN Apr 15, 2017