DESIGN ENGINEER

As a design engineer on our Design team, you will have the opportunity to work with one of our product divisions to develop our next generation of best-in-class silicon products. Opportunities exist in the areas of circuits, high-level logic, and mixed-signal devices.

Circuit Designer: As a circuit-level designer, you may have the opportunity to participate in any of the following: Specification, Design, Schematic Capture, and Layout of CMOS circuits, simulation with Spice and behavioral mixed-signal simulators, development of analog and mixed-signal IP chip development with industry-leading CAD tools

Logic Designer: As a logic designer you may have the opportunity to participate in any of the following: design of high-level logic functions using Verilog, use of Design Compiler to implement those functions, solving timing, power, and speed issues with industry-leading CAD tools.

Mixed-Signal Designer: As part of the Mixed-Signal Development and Verification team, you will learn mixed-signal verification flow and contribute to the development of Cypress’ leading-edge mixed signal products. And, as part of the Design Team, you will contribute to and be responsible for implementation and verification of key DFT logic modules. You will also contribute in various tasks spanning the entire design process.

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RFIC Mask Design Engineer
RFIC Mask Design Engineer San Jose, CA, US Jun 27, 2017
San Jose, CA, US Jun 27, 2017
Director of NPI
Director of NPI Binan City, LAG, PH Jun 27, 2017
Binan City, LAG, PH Jun 27, 2017
Staff Elect Design Engr (WLAN PHY Design)
Staff Elect Design Engr (WLAN PHY Design) Bangalore, KA, IN Jun 27, 2017
Bangalore, KA, IN Jun 27, 2017
Prin Elect Design Engr (Physical Design)
Prin Elect Design Engr (Physical Design) Bangalore, KA, IN Jun 27, 2017
Bangalore, KA, IN Jun 27, 2017
Staff Elect Design Engr (Physical Design)
Staff Elect Design Engr (Physical Design) Bangalore, KA, IN Jun 27, 2017
Bangalore, KA, IN Jun 27, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Shanghai, 31, CN Jun 26, 2017
Shanghai, 31, CN Jun 26, 2017
Sr Elect Design Engr 1
Sr Elect Design Engr 1 Shanghai, 31, CN Jun 26, 2017
Shanghai, 31, CN Jun 26, 2017
Sr Elect Design Engr
Sr Elect Design Engr Shanghai, 31, CN Jun 26, 2017
Shanghai, 31, CN Jun 26, 2017
Sr Prin Systems Engr
Sr Prin Systems Engr San Jose, CA, US Jun 26, 2017
San Jose, CA, US Jun 26, 2017
RFIC Design Engineer
RFIC Design Engineer San Jose, CA, US Jun 24, 2017
San Jose, CA, US Jun 24, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr San Jose, CA, US Jun 24, 2017
San Jose, CA, US Jun 24, 2017
Sr MTS Architect
Sr MTS Architect San Jose, CA, US Jun 24, 2017
San Jose, CA, US Jun 24, 2017
Sr Staff Systems Engr (PHY)
Sr Staff Systems Engr (PHY) Bangalore, KA, IN Jun 24, 2017
Bangalore, KA, IN Jun 24, 2017
Prin Systems Engr (PHY)
Prin Systems Engr (PHY) Bangalore, KA, IN Jun 24, 2017
Bangalore, KA, IN Jun 24, 2017
Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Jun 23, 2017
Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Jun 23, 2017
Staff Elect Design Engr
Staff Elect Design Engr San Jose, CA, US Jun 22, 2017
San Jose, CA, US Jun 22, 2017
Principal Logic Verification Engineer
Principal Logic Verification Engineer Lynnwood, WA, US Jun 21, 2017
Lynnwood, WA, US Jun 21, 2017
Design Engineer
Design Engineer Martinsried, BY, DE Jun 21, 2017
Martinsried, BY, DE Jun 21, 2017
Sr Elect Design Engr
Sr Elect Design Engr Tel Aviv, TA, IL Jun 21, 2017
Tel Aviv, TA, IL Jun 21, 2017
Electrical Design Engineer Principal (ASIC Design, RTL, Front End) Bangalore, KA, IN Jun 21, 2017
Staff ASIC Design Engr
Staff ASIC Design Engr Tel Aviv, TA, IL Jun 21, 2017
Tel Aviv, TA, IL Jun 21, 2017
Sr Staff Software Engr (WLAN Device Driver, Wireless) Bangalore, KA, IN Jun 21, 2017
Sr Elect Design Engr 1
Sr Elect Design Engr 1 Lynnwood, WA, US Jun 21, 2017
Lynnwood, WA, US Jun 21, 2017
Prin System Validation Engr
Prin System Validation Engr Bangalore, KA, IN Jun 20, 2017
Bangalore, KA, IN Jun 20, 2017