DESIGN ENGINEER

As a design engineer on our Design team, you will have the opportunity to work with one of our product divisions to develop our next generation of best-in-class silicon products. Opportunities exist in the areas of circuits, high-level logic, and mixed-signal devices.

Circuit Designer: As a circuit-level designer, you may have the opportunity to participate in any of the following: Specification, Design, Schematic Capture, and Layout of CMOS circuits, simulation with Spice and behavioral mixed-signal simulators, development of analog and mixed-signal IP chip development with industry-leading CAD tools

Logic Designer: As a logic designer you may have the opportunity to participate in any of the following: design of high-level logic functions using Verilog, use of Design Compiler to implement those functions, solving timing, power, and speed issues with industry-leading CAD tools.

Mixed-Signal Designer: As part of the Mixed-Signal Development and Verification team, you will learn mixed-signal verification flow and contribute to the development of Cypress’ leading-edge mixed signal products. And, as part of the Design Team, you will contribute to and be responsible for implementation and verification of key DFT logic modules. You will also contribute in various tasks spanning the entire design process.

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Sr Prin Systems Engr
Sr Prin Systems Engr San Jose, CA, US Aug 23, 2017
San Jose, CA, US Aug 23, 2017
Sr Elect Design Engr
Sr Elect Design Engr Shanghai, 31, CN Aug 23, 2017
Shanghai, 31, CN Aug 23, 2017
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Shanghai, 31, CN Aug 23, 2017
Shanghai, 31, CN Aug 23, 2017
Staff Elect Design Engr
Staff Elect Design Engr Shanghai, 31, CN Aug 23, 2017
Shanghai, 31, CN Aug 23, 2017
Sr Staff Systems Engr
Sr Staff Systems Engr San Jose, CA, US Aug 22, 2017
San Jose, CA, US Aug 22, 2017
Prin Mask Design Engr
Prin Mask Design Engr Penang, 07, MY Aug 21, 2017
Penang, 07, MY Aug 21, 2017
Prin Systems Engr (PHY)
Prin Systems Engr (PHY) Bangalore, KA, IN Aug 21, 2017
Bangalore, KA, IN Aug 21, 2017
Sr MTS Architect
Sr MTS Architect San Jose, CA, US Aug 21, 2017
San Jose, CA, US Aug 21, 2017
Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Aug 20, 2017
Senior Design Engineer (IP/SoC Verification, OVM, UVM, System Verilog) Langen, HE, DE Aug 20, 2017
Sr Staff Software Engr (WLAN Device Driver, Wireless) Bangalore, KA, IN Aug 18, 2017
Electrical Design Engineer Principal (ASIC Design, RTL, Front End) Bangalore, KA, IN Aug 18, 2017
Principal Logic Verification Engineer
Principal Logic Verification Engineer Lynnwood, WA, US Aug 18, 2017
Lynnwood, WA, US Aug 18, 2017
Sr Elect Design Engr 1
Sr Elect Design Engr 1 Lynnwood, WA, US Aug 18, 2017
Lynnwood, WA, US Aug 18, 2017
Staff ASIC Design Engr
Staff ASIC Design Engr Tel Aviv, TA, IL Aug 18, 2017
Tel Aviv, TA, IL Aug 18, 2017
Sr Elect Design Engr
Sr Elect Design Engr Tel Aviv, TA, IL Aug 18, 2017
Tel Aviv, TA, IL Aug 18, 2017
Sr Elect Design Engr 1
Sr Elect Design Engr 1 Lynnwood, WA, US Aug 18, 2017
Lynnwood, WA, US Aug 18, 2017
Staff Mask Design Engr 1
Staff Mask Design Engr 1 Bangalore, KA, IN Aug 17, 2017
Bangalore, KA, IN Aug 17, 2017
Prin System Validation Engr
Prin System Validation Engr Bangalore, KA, IN Aug 17, 2017
Bangalore, KA, IN Aug 17, 2017
Sr MTS Elect Design Engr
Sr MTS Elect Design Engr San Jose, CA, US Aug 17, 2017
San Jose, CA, US Aug 17, 2017
Elect Design Engr
Elect Design Engr San Jose, CA, US Aug 16, 2017
San Jose, CA, US Aug 16, 2017
Staff/Senior Staff Mask Design Engr (Analog/Mixed Signal Layout, Mask Design) Bangalore, KA, IN Aug 15, 2017
Sr Staff Elect Design Engr (SoC Verification, OVM, UVM) Bangalore, KA, IN Aug 15, 2017
Sr Elect Design Engr
Sr Elect Design Engr San Jose, CA, US Aug 15, 2017
San Jose, CA, US Aug 15, 2017
Sr MTS Architect
Sr MTS Architect San Jose, CA, US Aug 15, 2017
San Jose, CA, US Aug 15, 2017