DESIGN ENGINEER

As a design engineer on our Design team, you will have the opportunity to work with one of our product divisions to develop our next generation of best-in-class silicon products. Opportunities exist in the areas of circuits, high-level logic, and mixed-signal devices.

Circuit Designer: As a circuit-level designer, you may have the opportunity to participate in any of the following: Specification, Design, Schematic Capture, and Layout of CMOS circuits, simulation with Spice and behavioral mixed-signal simulators, development of analog and mixed-signal IP chip development with industry-leading CAD tools

Logic Designer: As a logic designer you may have the opportunity to participate in any of the following: design of high-level logic functions using Verilog, use of Design Compiler to implement those functions, solving timing, power, and speed issues with industry-leading CAD tools.

Mixed-Signal Designer: As part of the Mixed-Signal Development and Verification team, you will learn mixed-signal verification flow and contribute to the development of Cypress’ leading-edge mixed signal products. And, as part of the Design Team, you will contribute to and be responsible for implementation and verification of key DFT logic modules. You will also contribute in various tasks spanning the entire design process.

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Sr Prin Elect Design Engr
Sr Prin Elect Design Engr Austin, TX, US Feb 17, 2019
Austin, TX, US Feb 17, 2019
Lead Architect
Lead Architect Austin, TX, US Feb 17, 2019
Austin, TX, US Feb 17, 2019
Co-op Bachelors
Co-op Bachelors Cork, C, IE Feb 17, 2019
Cork, C, IE Feb 17, 2019
Co-op Bachelors
Co-op Bachelors Cork, C, IE Feb 17, 2019
Cork, C, IE Feb 17, 2019
Prin Elect Design Engr
Prin Elect Design Engr Dublin, D, IE Feb 15, 2019
Dublin, D, IE Feb 15, 2019
Elect Design Engr
Elect Design Engr Cork, C, IE Feb 15, 2019
Cork, C, IE Feb 15, 2019
Sr Prin Systems Engr
Sr Prin Systems Engr Hsinchui, HSQ, TW Feb 14, 2019
Hsinchui, HSQ, TW Feb 14, 2019
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Dublin, D, IE Feb 10, 2019
Dublin, D, IE Feb 10, 2019
Sr Elect Design Engr
Sr Elect Design Engr Dublin, D, IE Feb 9, 2019
Dublin, D, IE Feb 9, 2019
Sr Staff Systems Engr
Sr Staff Systems Engr Hsinchui, HSQ, TW Feb 9, 2019
Hsinchui, HSQ, TW Feb 9, 2019
Sr Prin Elect Design Engr
Sr Prin Elect Design Engr Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Sr Staff Elect Design Engr 1
Sr Staff Elect Design Engr 1 Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Principle Design Verification engg
Principle Design Verification engg Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Sr Staff Elect Design Engr
Sr Staff Elect Design Engr Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Prin Physical Design Engr
Prin Physical Design Engr Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Staff Elect Design Engr
Staff Elect Design Engr Bangalore, KA, IN Feb 9, 2019
Bangalore, KA, IN Feb 9, 2019
Sr Prin Applications Engr
Sr Prin Applications Engr Ylamlly, IS, FI Feb 8, 2019
Ylamlly, IS, FI Feb 8, 2019
Prin Elect Design Engr
Prin Elect Design Engr Cork, C, IE Feb 8, 2019
Cork, C, IE Feb 8, 2019
Mgr Design Engrg
Mgr Design Engrg Martinsried, BY, DE Feb 8, 2019
Martinsried, BY, DE Feb 8, 2019
Staff Verification Engr
Staff Verification Engr San Jose, CA, US Feb 8, 2019
San Jose, CA, US Feb 8, 2019
Sr Staff Verification Engr
Sr Staff Verification Engr San Jose, CA, US Feb 8, 2019
San Jose, CA, US Feb 8, 2019
Staff RTL Design Engr
Staff RTL Design Engr San Jose, CA, US Feb 8, 2019
San Jose, CA, US Feb 8, 2019
Prin RTL Design Engr
Prin RTL Design Engr San Jose, CA, US Feb 8, 2019
San Jose, CA, US Feb 8, 2019
Staff Analog Design Engr
Staff Analog Design Engr San Jose, CA, US Feb 8, 2019
San Jose, CA, US Feb 8, 2019