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Physical design STA lead

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Date: Apr 30, 2019

Location: Bangalore, KA, IN

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- [[16898]]

Job Description

1. This position is for STA and Timing Closure of complex, low power SoCs targeted for type-C, USB markets.

2. Candidate will work on constraints development for functional/test modes at pre/post layout stage.

3. Candidate will be responsible for timing analysis and convergence of large hierarchical designs.

4. Candidate will work closely with physical design team for timing/SI closure.

5. Candidate is expected to have deep understanding of low power design techniques and experience in MultiMode-MultiCorner timing analysis/closure.

Skills

1. Qualification - B.E./B.Tech. with 7-9 years of experience or M.E./MTech. with 5-7 years of experience and specialization in VLSI design

2. Strong hands-on technical experience in constraints development, timing analysis/closure of large SoCs

3. Expert user of industry standard tools for timing signoff

4. Experience in scripting languages (shell, perl, tcl) and Make flow

5. Understanding of 40nm/28nm technologies and associated timing/SI closure challenges

6. Experience in low-power synthesis and equivalence checks will be a plus

7. Must be well organized, methodical and detail oriented

 

Note

Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.



TO ALL RECRUITMENT AGENCIES:

Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.


Job Segment: Design Engineer, Engineering

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