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Staff Elect Design Engr

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Date: Nov 8, 2020

Location: Bangalore, KA, IN

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 22422

Job Description

Strong Back ground of ASIC Design For Test (DFT), Scan insertion fundamentals, ATPG pattern generation for various fault models such as Stuck-at, Transition Delay, Bridging and Cell Delay. Knowledge on debugging of DFT DRCs and Test coverage analysis to achieve PPM requirements. Good hands on experience on Memory Bist, Boundary Scan and Logic Bist test structures implementation.


Good problem solving and communictation skills.


Cypress is an Equal Employment Opportunity employer and does not discriminate in recruiting, hiring, training or promoting, on the basis of race, ethnicity, color, creed, religion, sex, sexual orientation, gender, gender identity, genetic information, national origin, physical or mental disability, pregnancy, medical condition, U.S. military or protected veteran status, union membership, or political affiliation.


Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

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