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Prin Mask Design Engr

Date: Jul 17, 2019

Location: Penang, 07, MY

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 17424

Job Description
  • Lead/co-lead the physical layout of hard IP design by working closely with cross functional team leader
  • Performing a range of back-end design activities, including floor-planning, clock and power distribution, place and route, timing analysis, physical verification, and chip integration
  • Perform clock tree synthesis to achieve balanced clock and timing ECO implementation
  • Working closely with circuit designers to solve tedious physical integration challenges.
Skills
  • Bachelor’s Degree in Electrical & Electronic Engineering with VLSI exposure or equivalent 5 - 10 years of job experience in layout design field with auto place & route (APR) experience
  • Knowledgeable in full-chip/block level place & route, floor planning and timing analysis and closure
  • Possess strong technical skill in physical layout development, debugging and problem solving skill
  • Good team player with excellent communication skills and good initiative at work
Note

Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.



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Job Segment: Engineer, Electrical, Design Engineer, Engineering

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