Prin RTL Design Engr

Requisition Id:- 16981

Responsibilities include:

• Participate in architecture definition and modeling.
• Follow industry standard specs and ensure IPs are kept up to date for compliance
• Define design partitioning for efficient IP implementation
• Review and provide feedback on IP verification plans.
• Work with Hard IP designers, verification and validation teams to produce thoroughly verified, robust IP
• Actively participate in post-silicon bring-up, validation and compliance testing.

Skills

Principal RTL Design Engineer must have following skills:

• Proven track record of taking one chip from product definition to production.
• Experience in complex ASIC design.
• Good understanding of ASIC design methodologies and flows.
• Very good understanding of standard ASIC design techniques, including:
  • Design partitioning and Hard IP interactions
  • Multiple async clock domain designs
  • Design for test
  • Clock/Reset
  • Power aware
• Very good working knowledge of:
  • Synthesis
  • STA
  • CDC
  • Lint
  • LEC
• Good problem solving skills.
• Work effectively with cross functional team
• Experience with silicon debug which include logic and custom Analog Blocks working together.
• Strong written and verbal communication skills.
• Self-motivated with the initiative to seek constant improvements in the design methodologies.
• The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, and be able to work within a diverse team environment.
• Expertise in USB/PCIe/micro-controller space is a plus.
• 5 - 7 years of experience.

Cypress is an Equal Employment Opportunity employer and does not discriminate in recruiting, hiring, training or promoting, on the basis of race, ethnicity, color, creed, religion, sex, sexual orientation, gender, gender identity, genetic information, national origin, physical or mental disability, pregnancy, medical condition, U.S. military or protected veteran status, union membership, or political affiliation.

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