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Staff Elect Design Engr

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Date: Jul 5, 2019

Location: San Jose, CA, US

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 17014

Job Description

Verification Engineer working in the Wired connectivity division on products meeting USB, PCIE and other connectivity standards:

Responsibilities include:

  • Participating in architecture definition and modeling.
  • Contributing to micro-architecture specification and reviews.
  • Reviewing industry standard specs and incorporating any changes into the verification plan to ensure compliance.
  • Defining verification strategy (constraint random, Formal, Directed etc.) for IP/Chip/System level verification.
  • Defining and implementing verification environment architecture and methodology development.
  • Driving block/chip/system level test plan development and execution.
  • Working with ASIC designers and architects to produce thoroughly verified, robust IP
  • Overseeing all verification for the IP/Chip/System and driving functional and code coverage closure.
  • Actively participating in post-silicon bringup, validation and compliance testing.
  • Actively participating in cross functional collaboration with design, software and hardware teams to ensure a successful product delivery.
  • Mentor other engineers and technically guide them.

 Verification Engineer must have following skills:

  • Proven track record of taking several chips in from product definition to production.
  • Experience in complex ASIC verification.
  • Good understanding of ASIC design and verification methodologies and flows.
  • Solid understanding of standard ASIC verification techniques, including:
    • Test planning
    • Testbench creation
    • Code and Functional coverage
    • Directed and random stimulus generation
    • Assertions
  • Solid understanding of verification methodologies and one or more of the following standard testbench languages:
    • SystemVerilog (OVM/UVM)
    • C/C++
    • Verilog PLI
  • Proficient in object oriented programming.
  • Experience with implementing constraint random verification methodology.
  • Good problem solving skills.
  • Knowledge of industry standards such as USB/PCIe is a plus.
  • Working effectively with both internal and external teams/customers is expected.
  • Experience with silicon debug which include logic and custom Analog Blocks working together.
  • Strong written and verbal communication skills.
  • In addition, be self-motivated with the initiative to seek constant improvements in the verification methodologies.
  • The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Experience in Industry: 10-15 years.


Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.


Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

Job Segment: Testing, Design Engineer, Technology, Engineering

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