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Sr Staff Analog Design Engr

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Date: Apr 7, 2019

Location: San Jose, CA, US

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 16974

Job Description

Sr. Staff Circuit Designer Responsibilities:

  • Working in the Wired connectivity division on products meeting USB/PCIE and other connectivity standards:
  • Participate in coordinating test and product engineering tasks for super speed products including support of test development.
  • Participate in design, integration & architecture development of 5G/10G SERDES circuits meeting performance, area, power and timescale constraints using state of the art EDA tools. 
  • Work with system and digital teams with product definition, chip integration, chip top level verification and system validation. 
  • Support DFT strategy and implementation. 
  • Silicon bring-up support of validation, production test and char teams.
  • Supervise layout and support junior engineers.


Sr. Staff should have the following skills:

  • Experience with 5G/10G-SERDES used with USB, PCIE, SATA etc.
  • Strong written and verbal communication skills.
  • Self-motivated with the initiative to seek constant improvements in the PHY design methodologies.
  • The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
  • Experience in dealing and designing complex IP's from different sources onto the same piece of silicon.
  • Very good understanding of transistor level analog integrated circuits, device physics and transmission-line characteristics
  • Design experience with analog modules such as PLL, high data rate transmitters, receivers and signal-conditioning/equalization etc. 
  • Experience with analysis of high data rate analog circuits & architectures, particular knowledge of jitter analysis and control - this is a key skill requirement.
  • Understand ESD/latch-up mechanism and be capable to debug the issue. 
  • Solid knowledge of EDA design tools and Cadence design environment.
  • Experienced in using 10Gbs test equipment is a plus.
  • Has taken at least one SERDES designs (> 5Gbs) into production with analog circuits.
  • Highly skilled in scheduling/budgeting of complex development programs, especially in product line planning.
  • A background in high frequency signal integrity modeling, understanding package substrate, PCB, back-plane and cabling design and tradeoffs is desired.
  • Data analysis (using MATLAB / Excel / Python / Perl) and test automation experience is highly desired.
  • Knowledge of USB/PCIE standards is a plus.
  • 7 - 10 years of experience.


Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.


Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

Job Segment: Engineer, Design Engineer, Data Analyst, Engineering, Data

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