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Elect Design Engr

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Date: May 8, 2019

Location: Shanghai, 31, CN

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 15250

Job Description

Graduate level design engineering position for logic verification and HDL design entry of system on chip (SOC) projects.

Skills

  1. logic verification flows including constrained random, transaction level modelling, pseudo random techniques, and assertion based verification.
  2. In addition to logic verification knowledge, they must be familiar with logic design flows including sub-system architecture (pipeline, bus architecture, comm interfaces, etc.), design entry, low power techniques, synthesis, place & route, static timing analysis, formal verification and logical equivalence checking.
  3. Desired knowledge includes C, C++, System C, System Verilog/OVM/UVM, Makefiles, C-shell scripts, Perl, Unix / Linux, MS office products (Word, Excel, PowerPoint, Project). The ideal candidate has a broad range of experience using multiple languages & tools.

Note

Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.

 

TO ALL RECRUITMENT AGENCIES:

Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.


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