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Sr Staff Elect Design Engr 1 1

Date: Aug 13, 2019

Location: Shanghai, 31, CN

Company: Cypress Semiconductor Corporation

Job Id

Requisition Id:- 17681

Job Description
  • Responsible for full chip verification, including verification architecture, verification requirement generation, test bench coding and coverage closure.
  • Develop UVM based full chip level verification environment and involved in IP level verification.
  • SoC level verification, including subsystem VIP integration, full chip tests coding and regression.    
  • Power aware verification with UPF.
  • SoC gate level verification.
  • Promote IP level DFT vector to chip level, run simulation and debug.
  • As a key role of verification team, contribute to improve the productivity of the team.
  • Good knowledge on full cycle of digital verification.
  • Good knowledge on System Verilog.
  • Experience with EDA tools for digital verification.
  • Experience with UVM and OVM.
  • Good communication skill, and fluent English
  • Verification project team management experience
  • Good team player and strong sense of responsibility to deliver on time. 

Cypress is an Equal Employment Opportunity employer and does not discriminate in recruiting, hiring, training or promoting, on the basis of race, ethnicity, color, creed, religion, sex, sexual orientation, gender, gender identity, genetic information, national origin, physical or mental disability, pregnancy, medical condition, U.S. military or protected veteran status, union membership, or political affiliation.


Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Job Segment: Design Engineer, Engineering

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