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Prin ASIC Design Engr

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Date: May 27, 2019

Location: Tel Aviv, TA, IL

Company: Cypress Semiconductor Corporation

Job ID

Requisition Id:- 7141

Job Description

Senior Place & Route / Backend Engineer

Position summary

  • In-depth knowledge of RTL to GDSII flow
  • Experience in PnR flow (Synth to GDSII), Floor planning, IOs, IPs, Power grid/domains(UPF), Place, CTS and route.
  • Experience in Cadence environment, Innovus, Virtuoso, Calibre verification – advantage.


Position Qualifications

  • Self-learning abilities
  • Team player
  • Scripting in perl, tcl and cshell – advantage
  • Technical management abilities – advantage
  • >5 years of experience in the semiconductor industry - Desirable.


Cypress is an Equal Employment Opportunity/Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, physical or mental disability, or status as a Protected Veteran.



Cypress Semiconductor does not accept unsolicited agency resumes. Please do not forward resumes to our jobs alias, Cypress Semiconductors employees or any other company location. Cypress Semiconductor is not responsible for any fees related to unsolicited resumes.

Job Segment: Design Engineer, Engineering

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